This invention relates to data storage systems and more particularly to data storage systems adapted to store data in, and retrieve data from, a bank of disk drives through a high speed cache or global memory interface disposed between the bank of disk drives and a host computer.
As is known in the art, large mainframe, or host computer systems require large capacity data storage systems. These large computer systems generally include data processors which perform many operations on data introduced to the computer system through peripherals including the data storage system. The results of these operations are output to peripherals, including the storage system.
One type of data storage system is a magnetic disk storage system. Here a bank of disk drives and the main frame computer system are coupled together through an interface. The interface includes CPU, or xe2x80x9cfront endxe2x80x9d, controllers (or directors) and xe2x80x9cback endxe2x80x9d disk controllers (or directors). The interface operates the controllers (or directors) in such a way that they are transparent to the computer. That is, data is stored in, and retrieved from, the bank of disk drives in such a way that the mainframe computer system merely thinks it is operating with one mainframe memory. One such system is described in U.S. Pat. No. 5,206,939, entitled xe2x80x9cSystem and Method for Disk Mapping and Data Retrievalxe2x80x9d, inventors Moshe Yanai, Natan Vishlitzky, Bruno Alterescu and Daniel Castel, issued Apr. 27, 1993, and assigned to the same assignee as the present invention.
As described in such U.S. Patent, the interface may also include, in addition to the CPU controllers (or directors) and disk controllers (or directors), addressable cache memories. The cache memory is a semiconductor memory and is provided to rapidly store data from the main frame computer system before storage in the disk drives, and, on the other hand, store data from the disk drives prior to being sent to the main frame computer. The cache memory being a semiconductor memory, as distinguished from a magnetic memory as in the case of the disk drives, is much faster than the disk drives in reading and writing data.
The CPU controllers, disk controllers and cache memory are interconnected through a backplane printed circuit board. More particularly, disk directors are mounted on disk director printed circuit boards. CPU directors are mounted on CPU controller printed circuit boards. And, cache memories are mounted on cache memory printed circuit boards. The disk director, CPU director and cache memory printed circuit boards plug into the backplane printed circuit board. In order to provide data integrity in case of a failure in a controller, the backplane printed circuit board has a pair of buses. One set the disk controllers is connected to one bus and another set of the disk controllers is connected to the other bus. Likewise, one set the CPU directors is connected to one bus and another set of the CPU directors is connected to the other bus. The cache memories are connected to both buses. Each one of the buses provides data, address and control information. Thus, the use of two buses provides a degree of redundancy to protect against a total system failure in the event that the controllers, or disk drives connected to one bus fail. Further, the use of two buses increases the data transfer bandwidth of the system compared to a system having a single bus. A four bus system is described in co-pending patent application Ser. No. 09/223,115 filed Dec. 30, 1998, entitled Data Storage Systems, inventors Tuccio et al., now U.S. Pat. No. 6,289,401 issued Sep. 11, 2001 assigned to the same assignee as the present invention, the entire subject matter thereof being incorporated herein by reference.
As noted above, the directors and cache memories are on printed circuit boards which plug into the backplane. As is also known in the art, the front end directors may be coupled to the host computer through a variety of front-end adapters, such as SCSI, fibre channel, Enterprise Systems Connection (ESCON), etc. For example, referring to FIG. 1, a front end director printed circuit board adapted for use in the two bus system described above, is shown coupled to an ESCON front-end adapter. It is noted that the front-end adapter has a pair of ports H1 and H2 adapted to couple to a pair of host computer ports. It is noted that the adapter is itself a printed circuit board which plugs into one side or the backplane as described in the above-referenced co-pending patent application for the four bus configuration. As described in such patent application, the director printed circuit board plugs into the opposite side of the printed circuit board.
Referring to FIG. 1, the two bus system described above is shown. An exemplary one of the front end adapters used in such system is shown in FIG. 2 to include a pair of optical interfaces each of which is coupled to a gate array. Each gate array, and the optical interface coupled thereto, is controlled by a CPU on the adapted board. The gate array, under control of its CPU, controls the flow of data between the front end director and the host computer. Thus, with such an arrangement, there are two independent data channels, Channel A and Channel B, between the host computer and each controller printed circuit board.
The control of data between the front end adapted board and the global cache memory connected to the director board, is through a pair of CPUs on the director board. These director board CPUs provide such control through communication with a corresponding one of the pair CPUs on the adapter board. The communication is through a corresponding one of a pair of shared memories, as indicated. It is noted that the two gate arrays in the director board are coupled to the global cache memory through a common data channel, here an SD I/O bus. The shared data channel includes a dual port RAM and an EDAC. as described in U.S. Pat. No. 5,890,207 entitled High Performance Integrated Cache Storage Device, inventors Sne et al, issued Mar. 30, 1999, assigned to the same assignee as the present invention the entire subject matter thereof being incorporated herein by reference. Arbitration for the common channel (i.e., for the SD I/O bus) is through a lower machine, as described in U.S. Pat. No. 5,890,207. Arbitration for the port of the dual port RAM (i.e., the port connected to the EDAC and the port connected to the global cache memory) is through the upper machine, as described in U.S. Pat. No.5,890,207.
In operation, and considering data passing from the host computer to the cache memory, the front end adapter gate array configures the data into, here 32 bit memory data words. The director CPUs package the 32 bit data words into here 64 bit memory data words. Requests for the SD I/O bus from the pair of director gate arrays are arbitrated by the lower machine via control signals ARB SD I/O, as indicated. The lower machine controls the EDAC and the dual port RAM. The start address for the data to be stored in the global cache memory is provided by address gate arrays under the control of the director CPUs and the lower machine. Further, considering, for example, that Channel A data is being processed by the EDAC and the data is then presented to the Channel B during such processing of the Channel A data, the lower machine prevents the data in Channel B from passing to the EDAC until completion of the processing of the Channel A data. The passing of data from the global cache memory to the host computer is by reciprocal operation.
Referring now to FIG. 3, another front end adapter/front end director configuration is shown for use the with two bus arrangement described above in connection with FIG. 1. Here, however, there are four ports H1, H2, H3 and H4 connecting the front end adapter to the host computer. While the director operates as described above in connection with FIG. 2, here there are four optic interfaces connected to the four ports H1, H2, H3 and H4, as indicated. Again there are only two gate arrays in the front end adapter each controlled by a corresponding one of the pair of front end adapter board CPUs. Here again there are only two independent data channels, Channel A and Channel B. Thus, while there are here four ports for connection to the host computer, there are still only two independent data channels, Channel A and Channel B (i.e., arbitration is required between ports H1 and H2 for Channel A and arbitration between ports H3 and H4 for Channel B).
Referring now to FIG. 4, a front end adapted and front end director arrangement is shown adapted for use in the four bus arrangement described in the above-referenced co-pending patent application. As described in such co-pending patent application, each director is coupled to a pair of the four busses. One of such busses is coupled to a xe2x80x9chigh addressxe2x80x9d memory section (MH) of the global cache memory and the other bus is coupled to a xe2x80x9clow addressxe2x80x9d (ML) memory section of the global cache memory. It is first noted that the front end adapter is the same as that described above in connection with FIG. 3. Here, however, the director has two EDACs and thus a pair of data channels, XSD I/O and YSD I/O, as indicated. Thus, here data Channel A is coupled to a first one of the pair of EDACs via the XSD I/O bus and data Channel B is coupled to the other one of the pair of EDACs though the YSD I/O bus, as indicated. Each EDAC is coupled to a corresponding one of a pair of dual port RAMs, as shown. The dual port RAMS are coupled to the xe2x80x9chigh addressxe2x80x9d memory section (MH) of the global cache memory or the xe2x80x9clow addressxe2x80x9d (ML) though transceivers (XCVRs) under the control of the upper machine, as indicated. Thus, as in the case of the configuration described above in connection with FIG. 3, while each front end director board has four ports with which to connect to the host computer, there are only two independent data channels, i.e., Channel A and Channel B. Thus, arbitration is required between ports H1 and H2 for Channel A and arbitration between ports H3 and H4 for Channel B), as indicated.
It should be noted that in all the configurations described above in connection with FIGS. 1 through 4, the CPUs start the transfer of data, stop the transfer of data and monitors the transfer of data; however, the CPUs do not actually move the data. Thus, the gate arrays move the data and thus the transfer of data to, and from, the cache memory is a DMA (direct memory access) transfer.
In accordance with the present invention, a system is provided having a memory with a plurality of contiguous memory regions. A plurality of processors is provided, each one of such processors being associated with a corresponding one of the memory regions. Each one of the processors provides a plurality of sets of processor addresses, the addresses each one of such sets having a series of used addresses and a series of reserve addresses, the last used address in one of the sets being separated from the first used address in another sets by a gap of addresses, G. A translator is included for mapping addresses fed thereto from the processors into the memory addresses, such mapping being in accordance with the gap G to map each one of the sets of used processor addresses provided by each of the processors into the corresponding one of the contiguous memory regions.
In accordance with another feature of the invention, a system is provided wherein a memory having a plurality of contiguous processor memory regions. A plurality of processors is included, each one of such processors being associated with a corresponding one of the processor memory regions. Each one of the processors provides a plurality of sets of successive processor addresses, the addresses in each one of such sets having a series of used addresses and a successive series of reserve addresses, the last used address in one of the sets being separated from the first used address in the next successive set of addresses by a gap of addresses, G. Each one of the used addresses in the sets of processor addresses corresponds to one of the processor memory regions. The addresses provided by each one of the processors for the set of processor addresses corresponding to the same processor memory region are different. A plurality of personal address translators is included. Each one of the personal translators is fed by a corresponding one of the processors. The translators map the processor addresses fed thereto to virtual addresses. The virtual addresses have a plurality of sets of virtual address regions. Each virtual address region corresponds to one of the processor memory regions. The personal translators map the set of processor addresses corresponding to the same processor memory region to the corresponding one of the sets of virtual address regions. A common address translator is fed by the virtual addresses, for mapping the virtual addresses fed thereto to the memory addresses, such mapping being in accordance with the gap G to map each one of the sets of used processor addresses provided by each of the processors into the corresponding one of the contiguous processor memory regions.
In one embodiment, the memory has a shared memory region contiguous to the plurality of processor memory regions. Each one of the processor is adapted to provide shared memory region address for storing data in the shared memory region or for retrieving data stored in such shared memory region at the provided shared memory region address. Each one of such processors provides such shared memory region address over the same range of processor addresses. The personal address translators maps the processor shared memory addresses to the a common range of the virtual addresses. The common address translator maps the virtual shared memory address into the shared memory region.
In accordance with one embodiment, a system includes a memory having a plurality of memory addresses. The memory is adapted to store data in such memory addresses, such plurality of memory addresses having a plurality of contiguous processor memory regions. A plurality of processors is included. Each one of such processors is associated with a corresponding one of the processor memory regions. Each one of such processors is adapted to provide processor addresses for storing data in the one of the processor memory regions corresponding such one of the processors at the memory addressees corresponding to such provided processor addresses or for retrieving data stored in such memory at the any one of the plurality of processor memory regions at the memory addresses corresponding to such provided processor addresses. Each one of such processors provides such processor address over the same range of processor addresses. The range of processor addresses has a plurality of sets of successive processor addresses. Each one of such sets has a series of used addresses and a successive series of reserve addresses. The last used address in one of the sets is separated from the first used address in the next successive set of addresses by a gap of addresses, G. Each one of the used addresses in the sets of processor addresses corresponding to one of the processor memory regions. The sets of processor addresses provided by one of the processors are different from the sets of processor addresses corresponding to another one of the processor. A plurality of personal address translators is included. Each one of the personal address translators is fed the processor address of a corresponding one of the processors for mapping the processor addresses fed thereto by such one of the processors to corresponding virtual addresses, such virtual addresses having a plurality of sets of virtual addresses. Each set of virtual addresses corresponds to one of the processor memory regions, the personal translators mapping the set of processor from the same processor to the same set of virtual addresses. A common address translator is fed by the virtual addresses mapped by the plurality of personal address translators, for mapping the virtual addresses fed thereto to the memory addresses, such mapping being in accordance with the gap G to map the range of processor addresses provided by each of the processor into the memory addresses of the corresponding one of the contiguous processor memory regions.